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ISQED
2007
IEEE
179views Hardware» more  ISQED 2007»
14 years 1 months ago
Cross Layer Error Exploitation for Aggressive Voltage Scaling
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used t...
Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Ku...
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
14 years 1 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
14 years 1 months ago
Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization
Model order reduction plays a key role in determining VLSI system performance and the optimization of interconnects. In this paper, we develop an accurate and provably passive met...
Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud
ISQED
2007
IEEE
372views Hardware» more  ISQED 2007»
14 years 1 months ago
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit
Problems in computational finance share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound nonlinearity, stringent accura...
Amith Singhee, Rob A. Rutenbar
ISQED
2007
IEEE
197views Hardware» more  ISQED 2007»
14 years 1 months ago
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
Toshinori Sato, Yuji Kunitake