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ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
14 years 1 months ago
Automated silicon debug data analysis techniques for a hardware data acquisition environment
Abstract—Silicon debug poses a unique challenge to the engineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overc...
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas...
ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
14 years 1 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen
ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
13 years 10 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 10 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
13 years 10 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim