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ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
14 years 3 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
ISSS
1997
IEEE
107views Hardware» more  ISSS 1997»
14 years 3 months ago
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning
Partitioning a system among multiple input and output pin I O limited packages is a widely researched and hard to solve problem. We previously described a new approach yielding ...
Frank Vahid
ISSS
1997
IEEE
105views Hardware» more  ISSS 1997»
14 years 3 months ago
Co-Emulation and Debugging of HW/SW-Systems
In this paper we present a method that allows to observe and control the emulation of communicating systems consisting of hardware and software parts. The approach provides the ab...
Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel
ISSS
1997
IEEE
128views Hardware» more  ISSS 1997»
14 years 2 months ago
Architectural Exploration and Optimization of Local Memory in Embedded Systems
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for explo...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
14 years 3 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran