Sciweavers

23 search results - page 2 / 5
» isvlsi 2008
Sort
View
ISVLSI
2008
IEEE
117views VLSI» more  ISVLSI 2008»
14 years 1 months ago
In Situ Design of Register Operations
We present methods to design programs or electronic circuits, for performing any operation on k registers of any sizes in a processor, in such a way that one uses no other working...
Serge Burckel, Emeric Gioan
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
14 years 1 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
14 years 1 months ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
ISVLSI
2008
IEEE
152views VLSI» more  ISVLSI 2008»
14 years 1 months ago
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
Julien Dalmasso, Érika F. Cota, Marie-Lise ...
ISVLSI
2008
IEEE
161views VLSI» more  ISVLSI 2008»
14 years 1 months ago
Impact of Technology Scaling on Digital Subthreshold Circuits
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...