Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways

The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90nm process, we show that choosing higher Vth, Tox and adding one spare way to a 4-way 16KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
• Keywords: Cache, Cache Power Consumption, Cache Reduces Leakage, ISVLSI 2008, VLSI