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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 12 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
KR
2000
Springer
15 years 9 months ago
An Environment for Merging and Testing Large Ontologies
Large-scale ontologies are becoming an essential component of many applications including standard search (such as Yahoo and Lycos), ecommerce (such as Amazon and eBay), configura...
Deborah L. McGuinness, Richard Fikes, James Rice, ...
AFRICACRYPT
2008
Springer
16 years 6 days ago
Improving Integral Attacks Against Rijndael-256 Up to 9 Rounds
Rijndael is a block cipher designed by V. Rijmen and J. Daemen and it was chosen in its 128-bit block version as AES by the NIST in October 2000. Three key lengths - 128, 192 or 25...
Samuel Galice, Marine Minier
MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
15 years 11 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
GD
1998
Springer
15 years 10 months ago
Using Graph Layout to Visualize Train Interconnection Data
We consider the problem of visualizing interconnections in railway systems. Given time tables from systems with thousands of trains, we are to visualize basic properties of the co...
Ulrik Brandes, Dorothea Wagner