Sciweavers

34 search results - page 6 / 7
» micro 1998
Sort
View
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
14 years 3 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
14 years 3 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck
MICRO
2007
IEEE
113views Hardware» more  MICRO 2007»
13 years 10 months ago
The High Cost of a Cheap Lesson
y abstract, it is grounded in the experience of many markets. As I will illustrate, it explains much strategic behavior. Information spreads With a bit of effort, any technically s...
Shane Greenstein
VL
1998
IEEE
130views Visual Languages» more  VL 1998»
14 years 3 months ago
SAM - An Animated 3D Programming Language
This article presents the animated visual 3D programming language SAM (Solid Agents in Motion) for parallel systems specification and animation. A SAM program is a set of interact...
Christian Geiger, Wolfgang Müller 0003, Walde...
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
14 years 3 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie