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MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 4 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 4 months ago
Finding concurrency bugs with context-aware communication graphs
Incorrect thread synchronization often leads to concurrency bugs that manifest nondeterministically and are difficult to detect and fix. Past work on detecting concurrency bugs ...
Brandon Lucia, Luis Ceze
MICRO
2009
IEEE
326views Hardware» more  MICRO 2009»
14 years 4 months ago
DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage
Data structures define how values being computed are stored and accessed within programs. By recognizing what data structures are being used in an application, tools can make app...
Changhee Jung, Nathan Clark
MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
14 years 4 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 4 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002