Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
Jan Willem van den Brand, Calin Ciordas, Kees Goos...
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
Zied Marrakchi, Hayder Mrabet, Christian Masson, H...
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...