In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
- In this paper, we analyze the impact of network contention on the application mapping for tile-based Networkon-Chip (NoC) architectures. Our main theoretical contribution consist...
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
In this paper, we propose a run-time strategy for allocating the application tasks to platform resources in homogeneous Networks-on-Chip (NoCs). As novel contribution, we incorpor...
Design-time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. This drives the development of run-time adaptive s...