Sciweavers

61 search results - page 10 / 13
» nocs 2010
Sort
View
NOCS
2010
IEEE
13 years 6 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
LCTRTS
2010
Springer
13 years 6 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
NOCS
2010
IEEE
13 years 7 months ago
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
Michael N. Horak, Steven M. Nowick, Matthew Carlbe...
VLSI
2010
Springer
13 years 7 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...