In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua ...
An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage valu...
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...