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ARITH
2007
IEEE
14 years 2 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
14 years 2 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
CVPR
2007
IEEE
14 years 1 months ago
Matrix-Structural Learning (MSL) of Cascaded Classifier from Enormous Training Set
Aiming at the problem when both positive and negative training set are enormous, this paper proposes a novel Matrix-Structural Learning (MSL) method, as an extension to Viola and ...
Shengye Yan, Shiguang Shan, Xilin Chen, Wen Gao, J...
DASFAA
2007
IEEE
174views Database» more  DASFAA 2007»
14 years 1 months ago
Efficient Holistic Twig Joins in Leaf-to-Root Combining with Root-to-Leaf Way
Finding all the occurrences of a twig pattern on multiple elements in an XML document is a core operation for efficient evaluation of XML queries. Holistic twig join algorithms, Tw...
Guoliang Li, Jianhua Feng, Yong Zhang, Lizhu Zhou
DATE
2007
IEEE
174views Hardware» more  DATE 2007»
14 years 1 months ago
ATLAS: a chip-multiprocessor with transactional memory support
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy T...