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ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Ko...
PE
2007
Springer
130views Optimization» more  PE 2007»
13 years 7 months ago
Performability analysis of clustered systems with rejuvenation under varying workload
This paper develops time-based rejuvenation policies to improve the performability measures of a cluster system. Three rejuvenation policies, namely standard rejuvenation, delayed...
Dazhi Wang, Wei Xie, Kishor S. Trivedi
PARELEC
2006
IEEE
14 years 1 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 1 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
NA
2006
84views more  NA 2006»
13 years 7 months ago
Fast Moreau envelope computation I: numerical algorithms
Abstract. The present article summarizes the state of the art algorithms to compute the discrete Moreau envelope, and presents a new linear-time algorithm, named NEP for NonExpansi...
Yves Lucet