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TCAD
1998
82views more  TCAD 1998»
13 years 9 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
TCAD
1998
119views more  TCAD 1998»
13 years 9 months ago
A controller redesign technique to enhance testability of controller-data path circuits
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
TCAD
1998
127views more  TCAD 1998»
13 years 9 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
TCAD
1998
96views more  TCAD 1998»
13 years 9 months ago
Diagnosis of clustered faults and wafer testing
—A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to a...
Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thula...
TCAD
1998
95views more  TCAD 1998»
13 years 9 months ago
A framework for comparing models of computation
—We give a denotational framework (a “meta model”) within which certain properties of models of computation can be compared. It describes concurrent processes in general term...
Edward A. Lee, Alberto L. Sangiovanni-Vincentelli