—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
—A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to a...
Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thula...
—We give a denotational framework (a “meta model”) within which certain properties of models of computation can be compared. It describes concurrent processes in general term...