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TCAD
1998
13 years 9 months ago
1998
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
TCAD
1998
13 years 9 months ago
1998
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
TCAD
2002
13 years 9 months ago
2002
Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local character...
TCAD
2002
13 years 9 months ago
2002
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
TCAD
2002
13 years 9 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...