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ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
14 years 1 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
14 years 1 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
14 years 1 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
KBSE
1998
IEEE
14 years 1 months ago
Automated Integrative Analysis of State-based Requirements
Statically analyzing requirements specifications to assure that they possess desirable properties is an important activity in any rigorous software development project. The analys...
Barbara J. Czerny, Mats Per Erik Heimdahl
METRICS
1998
IEEE
14 years 1 months ago
Getting a Handle on the Fault Injection Process: Validation of Measurement Tools
In any manufacturing environment, the fault injection rate might be considered one of the most meaningful criterion to evaluate the goodness of the development process. In our fie...
Sebastian G. Elbaum, John C. Munson