In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitive...
Ahmed Amine Jerraya, Amer Baghdadi, Damien Lyonnar...
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...