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VLSID
2010
IEEE
202views VLSI» more  VLSID 2010»
13 years 5 months ago
Processor Architecture Design Using 3D Integration Technology
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
Yuan Xie
VLSID
2010
IEEE
168views VLSI» more  VLSID 2010»
13 years 11 months ago
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
13 years 11 months ago
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Abstract—Microfluidics-based biochips are revolutionizing highthroughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the pre...
Krishnendu Chakrabarty
VLSID
2010
IEEE
181views VLSI» more  VLSID 2010»
13 years 11 months ago
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients
We propose a method for diagnosis of parametric faults in analog circuits using polynomial coefficients of the circuit model [15]. As a sequel to our recent work [14], where circ...
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
14 years 9 days ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...