The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
Abstract—Microfluidics-based biochips are revolutionizing highthroughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the pre...
We propose a method for diagnosis of parametric faults in analog circuits using polynomial coefficients of the circuit model [15]. As a sequel to our recent work [14], where circ...
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...