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    VLSID
    2001
    IEEE
    98views VLSI» more  VLSID 2001»
    Complexity Of Minimum-Delay Gate Resizing
    16 years 3 months ago
    Complexity Of Minimum-Delay Gate Resizing
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    Supratik Chakraborty, Rajeev Murgai
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    VLSID
    2001
    IEEE
    82views VLSI» more  VLSID 2001»
    High Level Synthesis Of Multi-Precision Data Flow Graphs
    16 years 3 months ago
    High Level Synthesis Of Multi-Precision Data Flow Graphs
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    Vikas Agrawal, Anand Pande, Mahesh Mehendale
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    VLSID
    2001
    IEEE
    88views VLSI» more  VLSID 2001»
    Switching Noise Analysis Framework For High Speed Logic Families
    16 years 3 months ago
    Switching Noise Analysis Framework For High Speed Logic Families
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    Marco Delaurenti, Mariagrazia Graziano, Guido Mase...
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    VLSID
    2001
    IEEE
    104views VLSI» more  VLSID 2001»
    Partitioning Routing Area into Zones with Distinct Pins
    16 years 3 months ago
    Partitioning Routing Area into Zones with Distinct Pins
    Download  vlsicad.ucsd.edu
    Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhatt...
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    VLSID
    2001
    IEEE
    93views VLSI» more  VLSID 2001»
    A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers
    16 years 3 months ago
    A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers
    Download  soc.cs.nchu.edu.tw
    Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
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