Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

23

VLSID
2001
IEEE

favoriteEmaildiscussreport

82views VLSI» more VLSID 2001»

High Level Synthesis Of Multi-Precision Data Flow Graphs

14 years 11 months ago

High Level Synthesis Of Multi-Precision Data Flow Graphs

Download eprints.iisc.ernet.in

Vikas Agrawal, Anand Pande, Mahesh Mehendale

Real-time Traffic

Computer Architecture | Multi-Precision Data Flow | VLSID 2001 |

claim paper

Related Content

» A new technique for estimating lower bounds on latency for high level synthesis

» PowerManageable Scheduling Technique for Control Dominated HighLevel Synthesis

» Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Gra...

» Combined Control Flow Dominated and Data Flow Dominated HighLevel Synthesis

» Data path Configuration Time Reduction for Runtime Reconfigurable Systems

» Optimizing data flow graphs to minimize hardware implementation

» Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Des...

» Reducing the Complexity of ILP Formulations for Synthesis

» Layout driven data communication optimization for high level synthesis

Post Info
More Details (n/a)

Added	01 Dec 2009
Updated	01 Dec 2009
Type	Conference
Year	2001
Where	VLSID
Authors	Vikas Agrawal, Anand Pande, Mahesh Mehendale

Comments (0)