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35
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PATMOS
2004
Springer
138
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Modeling and Simulation
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PATMOS 2004
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Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
14 years 5 months ago
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ce.et.tudelft.nl
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana
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