Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic

The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Recycling Threshold Logic (CRTL). It is shown that compared to domino, the

• Type: Conference
• Year: 2004
• Where: PATMOS
• Authors: Peter Celinski, Derek Abbott, Sorin Cotofana
• Keywords: 4-bit Carry Generate, Delay Comparison, PATMOS 2004, Threshold Logic