VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
VLSID
2007
IEEE
14 years 12 months ago
2007
IEEE
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...