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VLSID
2006
IEEE
136views VLSI» more  VLSID 2006»
14 years 12 months ago
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
Simon Ogg, Bashir M. Al-Hashimi
VLSID
2006
IEEE
86views VLSI» more  VLSID 2006»
14 years 12 months ago
Partial Product Reduction Based on Look-Up Tables
In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices ...
F. Pujol López, Higinio Mora Mora, Jer&oacu...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 12 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 12 months ago
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasma...
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
14 years 12 months ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
14 years 12 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
VLSID
2006
IEEE
134views VLSI» more  VLSID 2006»
14 years 12 months ago
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and dis...
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
VLSID
2006
IEEE
108views VLSI» more  VLSID 2006»
14 years 12 months ago
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication
Amit Kumar 0002, Noriyuki Miura, Muhammad Muqsith,...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 12 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
VLSID
2006
IEEE
140views VLSI» more  VLSID 2006»
14 years 12 months ago
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis