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NOCS
2009
IEEE
14 years 6 months ago
Analysis of photonic networks for a chip multiprocessor using scientific applications
Gilbert Hendry, Shoaib Kamil, Aleksandr Biberman, ...
NOCS
2009
IEEE
14 years 6 months ago
Exploring concentration and channel slicing in on-chip network router
Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the t...
Prabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Al...
NOCS
2009
IEEE
14 years 6 months ago
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
Communication plays a crucial role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to simpli...
Luca P. Carloni, Partha Pande, Yuan Xie
NOCS
2009
IEEE
14 years 6 months ago
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
Daniele Ludovici, Alessandro Strano, Davide Bertoz...
NOCS
2009
IEEE
14 years 6 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
NOCS
2009
IEEE
14 years 6 months ago
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A virtual channel (VC) is allocated on a per-pack...
Young Hoon Kang, Taek-Jun Kwon, Jeff Draper
NOCS
2009
IEEE
14 years 6 months ago
Flow-aware allocation for on-chip networks
Current Virtual-Channel routers disregard potentially useful information about on-chip communication flows. This often leads to inefficient resource utilisation in existing Netwo...
Arnab Banerjee, Simon W. Moore
NOCS
2009
IEEE
14 years 6 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
NOCS
2009
IEEE
14 years 6 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...