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FORMATS
2004
Springer
13 years 11 months ago
The Influence of Durational Actions on Time Equivalences
The hierarchy of untimed equivalences is well understood for action-based systems. This is not the case for timed systems, where it is, for example, possible to detect concurrency ...
Harald Fecher
FORMATS
2004
Springer
13 years 11 months ago
Modeling and Verification of a Fault-Tolerant Real-Time Startup Protocol Using Calendar Automata
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...
Bruno Dutertre, Maria Sorea
FORMATS
2004
Springer
13 years 11 months ago
Some Progress in Satisfiability Checking for Difference Logic
Abstract. In this paper we report a new SAT solver for difference logic, a propositional logic enriched with timing constraints. The main novelty of our solver is a tighter integra...
Scott Cotton, Eugene Asarin, Oded Maler, Peter Nie...
FMCO
2004
Springer
123views Formal Methods» more  FMCO 2004»
13 years 11 months ago
rCOS: Refinement of Component and Object Systems
Abstract. We present a model of object-oriented and component-based refinement. For object-orientation, the model is class-based and refinement is about correct changes in the stru...
Zhiming Liu, Jifeng He, Xiaoshan Li
FMCO
2004
Springer
13 years 11 months ago
A Perspective on Component Refinement
Abstract. This paper provides an overview of an approach to coalgebraic modelling and refinement of state-based software components, summing up some basic results and introducing a...
Luís Soares Barbosa
FMCAD
2004
Springer
13 years 11 months ago
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
Orna Grumberg, Assaf Schuster, Avi Yadgar
FMCAD
2004
Springer
13 years 11 months ago
A Functional Approach to the Formal Specification of Networks on Chip
We present a functional approach, based on the ACL2 logic, for the specification of system on a chip communication architectures. Our decomposition of the communications allows the...
Julien Schmaltz, Dominique Borrione
FMCAD
2004
Springer
13 years 11 months ago
A Partitioning Methodology for BDD-Based Verification
The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this paper we advocate a methodology to handle this probl...
Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain,...
FMCAD
2004
Springer
13 years 11 months ago
Bloom Filters in Probabilistic Verification
Abstract. Probabilistic techniques for verification of finite-state transition systems offer huge memory savings over deterministic techniques. The two leading probabilistic scheme...
Peter C. Dillinger, Panagiotis Manolios
FMCAD
2004
Springer
13 years 11 months ago
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
Thao Dang, Alexandre Donzé, Oded Maler