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ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...
ASPDAC
2008
ACM
90views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Vertical via design techniques for multi-layered P/G networks
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...
Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Design space exploration for a coarse grain accelerator
- In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design s...
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zaman...
ASPDAC
2008
ACM
119views Hardware» more  ASPDAC 2008»
14 years 1 months ago
A stochastic local hot spot alerting technique
- With the increasing levels of variability in the behavior of manufactured nano-scale devices and dramatic changes in the power density on a chip, timely identification of hot spo...
Hwisung Jung, Massoud Pedram
ASPDAC
2008
ACM
93views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Ordered escape routing based on Boolean satisfiability
Abstract-- Routing for high-speed boards is largely a timeconsuming manual task today. In this work we consider the ordered escape routing problem which is a key problem in boardle...
Lijuan Luo, Martin D. F. Wong
ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung
ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Power grid analysis benchmarks
ACT Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent expe...
Sani R. Nassif
ASPDAC
2008
ACM
69views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Fast, quasi-optimal, and pipelined instruction-set extensions
Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, th...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ASPDAC
2008
ACM
99views Hardware» more  ASPDAC 2008»
14 years 1 months ago
1-cc computer using UWB-IR for wireless sensor network
Tatsuo Nakagawa, Masayuki Miyazaki, Goichi Ono, Ry...