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ISMVL
1991
IEEE
88views Hardware» more  ISMVL 1991»
14 years 3 months ago
On the Maximum Size of the Terms in the Realization of Symmetric Functions
Ratko Tosic, Ivan Stojmenovic, Masahiro Miyakawa
ISMVL
1991
IEEE
145views Hardware» more  ISMVL 1991»
14 years 3 months ago
The Abnormality Predicate
We suggest a new representation of defeasible entailment and specificity in the framework of default logic. The representation is based on augmenting the underlying classical lan...
Eric Neufeld
ISCA
1991
IEEE
121views Hardware» more  ISCA 1991»
14 years 3 months ago
IXM2: A Parallel Associative Processor
This paper describes a parallel associative processor, IXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors,...
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, N...
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
14 years 3 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
14 years 3 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
14 years 3 months ago
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai...
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
14 years 3 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram
ICCD
1991
IEEE
95views Hardware» more  ICCD 1991»
14 years 3 months ago
Fast Capacitance Extraction of General Three-Dimensional Structures
Keith Nabors, S. Kim, Jacob White, Stephen D. Sent...