This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be ...
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon S...
The analysis and measurement of current levels of software reuse are necessary to monitor improvements. This paper provides a framework for the derivation of measures of software ...
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...
To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in proce...
Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Jan...