As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet...
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...
- In routing, finding a rectilinear Steiner minimal tree (RSMT) is a fundamental problem. Today's design often contains rectilinear obstacles, like macro cells, IP blocks, and...
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...