Due to the extremely large sizes of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. It has been shown in [...
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
- Two challenges for the accurate prediction of GHz CMOS analog/RF building blocks are presented. Challenging the usage of new compact MOSFET models enhances the simulation accurac...
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a cir...
Shrirang K. Karandikar, Charles J. Alpert, Mehmet ...
Abstract-- This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that plac...
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...