A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be ...
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing a...
Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Ham...
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...