The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has...
This paper focuses on observability, one of the open issues in High-Level test generation. Three different approximate metrics for taking observability into account during RT-leve...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, the power supply transient...
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...