Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
This paper proposes a new method based on analytic signal theory for extracting both instantaneous and RMS sinusoidal jitter from PLL output signals. The method relies on the exte...
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma,...
Delay defects can escape detection during the normal production test flow, particularly if they do not affect any of the long paths included in the test flow. Some defect types ca...
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao...
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
Hardware duplication techniques are widely used for concurrent error detection in dependable systems to ensure high availability and data integrity. These techniques are vulnerabl...
Subhasish Mitra, Nirmal R. Saxena, Edward J. McClu...
Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy (TMR) is a widely used ...
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed metho...
Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailogl...