Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
Jeffrey Kang, Albert van der Werf, Paul E. R. Lipp...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...