This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...
Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulya...
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...