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    ASPDAC
    2007
    ACM
    79views Hardware» more  ASPDAC 2007»
    Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
    13 years 11 months ago
    Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
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    Stefan Disch, Christoph Scholl
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    ASPDAC
    2007
    ACM
    123views Hardware» more  ASPDAC 2007»
    Coupling-aware Dummy Metal Insertion for Lithography
    13 years 11 months ago
    Coupling-aware Dummy Metal Insertion for Lithography
    Download  domino.research.ibm.com
    As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
    Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua ...
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    ASPDAC
    2007
    ACM
    68views Hardware» more  ASPDAC 2007»
    System Architecture for Software Peripherals
    13 years 11 months ago
    System Architecture for Software Peripherals
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    Siddharth Choudhuri, Tony Givargis
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    ASPDAC
    2007
    ACM
    92views Hardware» more  ASPDAC 2007»
    New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
    13 years 11 months ago
    New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
    Download  www.cecs.uci.edu
    With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
    Ruiming Chen, Hai Zhou
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    ASPDAC
    2007
    ACM
    116views Hardware» more  ASPDAC 2007»
    DFM/DFY practices during physical designs for timing, signal integrity, and power
    13 years 11 months ago
    DFM/DFY practices during physical designs for timing, signal integrity, and power
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    Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-...
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    ASPDAC
    2007
    ACM
    110views Hardware» more  ASPDAC 2007»
    High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
    13 years 11 months ago
    High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
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    Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
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    ASPDAC
    2007
    ACM
    98views Hardware» more  ASPDAC 2007»
    Fixing Design Errors with Counterexamples and Resynthesis
    13 years 11 months ago
    Fixing Design Errors with Counterexamples and Resynthesis
    Download  www.eecs.umich.edu
    -- In this work we propose a new error-correction framework, called CoR
    Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
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    ASPDAC
    2007
    ACM
    116views Hardware» more  ASPDAC 2007»
    Safe Delay Optimization for Physical Synthesis
    13 years 11 months ago
    Safe Delay Optimization for Physical Synthesis
    Download  www.eecs.umich.edu
    -- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
    Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
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    ASPDAC
    2007
    ACM
    99views Hardware» more  ASPDAC 2007»
    DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
    13 years 11 months ago
    DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
    Download  www.ee.ucla.edu
    Abstract - This paper presents a fast and accurate global routing algorithm, DpRouter, based on two efficient techniques: (1) dynamic pattern routing (Dpr), and (2) segment movemen...
    Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, ...
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    ASPDAC
    2007
    ACM
    83views Hardware» more  ASPDAC 2007»
    Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
    13 years 11 months ago
    Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
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    Subhasis Banerjee, G. Surendra, S. K. Nandy
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