ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facili...
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
Noise immunity is becomingone of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the pr...
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they me...
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
ASYNC
1999
IEEE
14 years 5 months ago
1999
IEEE
We describe an extension of the virtual volume concept to multiple sensors. Data from multiple sensors are combined in real-time and mapped into a constantly updating three-dimens...