ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for hierarchical test. Based on a cel...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
As the deep sub-micron techniques evolving, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to the access limitations. ...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that ...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper addresses the problem of locating the stuckopen faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty s...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
We propose a methodology for non-intrusive design of concurrently self-testable FSMs. Unlike duplication schemes, wherein a replica of the original FSM acts as a predictor-compara...
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE
ATS
2002
IEEE
14 years 5 months ago
2002
IEEE