TC
2008
14 years 10 days ago
2008
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
SIGARCH
2008
14 years 11 days ago
2008
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
PE
2006
Springer
14 years 11 days ago
2006
Springer
In a multi-level cache such as those used for web caching, a hit at level l leads to the caching of the requested object in all intermediate caches on the reverse path (levels l -...
MICRO
2006
IEEE
14 years 11 days ago
2006
IEEE
CMPs enable simultaneous execution of multiple applications on the same platforms that share cache resources. Diversity in the cache access patterns of these simultaneously execut...
IJHPCA
2006
14 years 13 days ago
2006
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
CAL
2007
14 years 13 days ago
2007
— This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by mult...
ADHOC
2006
14 years 15 days ago
2006
Internet-based mobile ad hoc network (IMANETIMANET) is an emerging technique that combines a wired network (e.g. Internet) and a mobile ad hoc network (MANETMANET) for developing ...
DPD
2008
14 years 15 days ago
2008
The continuous partial match query is a partial match query whose result remains consistently in the client's memory. Conventional cache invalidation methods for mobile client...
ADHOC
2008
14 years 17 days ago
2008
Caching techniques can be used to reduce bandwidth consumption and data access delay in wireless ad hoc networks. When cache is used, the issue of cache consistency must be addres...
AAECC
2007
Springer
14 years 17 days ago
2007
Springer
Abstract. We present new performance models and a new, more compact data structure for cache blocking when applied to the sparse matrixvector multiply (SpM×V) operation, y ← y +...