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    CDES
    2006
    107views Hardware» more  CDES 2006»
    An Algorithm for Yield Improvement via Local Positioning and Resizing
    14 years 26 days ago
    An Algorithm for Yield Improvement via Local Positioning and Resizing
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    The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...
    Vazgen Karapetyan
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    CDES
    2006
    106views Hardware» more  CDES 2006»
    A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization
    14 years 26 days ago
    A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization
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    - Most of the direct-cover Boolean minimization techniques use a four step cyclic algorithm. First, the algorithm chooses an On-minterm; second, it generates the set of prime impli...
    Sirzat Kahramanli, Suleyman Tosun
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    CDES
    2006
    146views Hardware» more  CDES 2006»
    ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design
    14 years 26 days ago
    ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design
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    A neural network approach is presented for modeling and characterization of on-chip copper spiral inductors. The approach involves the creation of neural network models to map 3D ...
    Abby A. Ilumoka, Yeonbum Park
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    CDES
    2006
    118views Hardware» more  CDES 2006»
    New DSP Benchmark based on Selectable Mode Vocoder (SMV)
    14 years 26 days ago
    New DSP Benchmark based on Selectable Mode Vocoder (SMV)
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    Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance ...
    Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jia...
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    CDES
    2006
    249views Hardware» more  CDES 2006»
    Round-Robin Arbiter Design
    14 years 26 days ago
    Round-Robin Arbiter Design
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    - Round-robin has been used as a fair (non starvation) scheduling policy in many computer applications. This paper presents a novel hardware design of a round-robin arbiter without...
    Jinming Ge
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    CDES
    2006
    106views Hardware» more  CDES 2006»
    Reducing Memory References for FFT Calculation
    14 years 26 days ago
    Reducing Memory References for FFT Calculation
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    Fast Fourier Transform (FFT) is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication applications. many of t...
    Ayman Elnaggar, Mokhtar Aboelaze
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    CDES
    2006
    101views Hardware» more  CDES 2006»
    Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
    14 years 26 days ago
    Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
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    - Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
    Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
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    CDES
    2006
    240views Hardware» more  CDES 2006»
    Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
    14 years 26 days ago
    Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
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    Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
    Arun N. Chandorkar, Gurvinder Singh
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    CDES
    2006
    96views Hardware» more  CDES 2006»
    Bandwidth-Friendly Cache Hierarchy
    14 years 26 days ago
    Bandwidth-Friendly Cache Hierarchy
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    Anasua Bhowmik, Mohamed M. Zahran
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    CDES
    2006
    76views Hardware» more  CDES 2006»
    Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations
    14 years 26 days ago
    Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations
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    Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, ...
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