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14 years 4 months ago
UP Electrical and Electronics Engineering Institute
The Institute's mission is to produce excellent, innovative and nationalistic engineers and to advance the field of electrical and electronics engineering. The undergr...
HPCA
2001
IEEE
14 years 7 months ago
Self-Tuned Congestion Control for Multiprocessor Networks
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S....
HPCA
2001
IEEE
14 years 7 months ago
Branch History Guided Instruction Prefetching
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson...
HPCA
2001
IEEE
14 years 7 months ago
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not ...
Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alo...
HPCA
2001
IEEE
14 years 7 months ago
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue...
Pierre Michaud, André Seznec
HPCA
2001
IEEE
14 years 7 months ago
Speculative Data-Driven Multithreading
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
Amir Roth, Gurindar S. Sohi
HPCA
2001
IEEE
14 years 7 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
HPCA
2001
IEEE
14 years 7 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
HPCA
2001
IEEE
14 years 7 months ago
A Delay Model and Speculative Architecture for Pipelined Routers
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
Li-Shiuan Peh, William J. Dally