Sciweavers

HPCA
2001
IEEE
14 years 7 months ago
Performance of Hardware Compressed Main Memory
A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically available memory. This ...
Bülent Abali, Dan E. Poff, Hubertus Franke, T...
HPCA
2002
IEEE
14 years 7 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
HPCA
2002
IEEE
14 years 7 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
HPCA
2002
IEEE
14 years 7 months ago
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
G. Edward Suh, Srinivas Devadas, Larry Rudolph
HPCA
2002
IEEE
14 years 7 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
HPCA
2002
IEEE
14 years 7 months ago
Modeling Value Speculation
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
Yiannakis Sazeides
HPCA
2002
IEEE
14 years 7 months ago
Bandwidth Adaptive Snooping
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, ...
HPCA
2002
IEEE
14 years 7 months ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
HPCA
2002
IEEE
14 years 7 months ago
Power Issues Related to Branch Prediction
This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy ...
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco B...