One of the popular design methodologies for power distribution networks (PDNs) is to identify a target impedance to be met across a broad frequency range. The methodology is based...
Xiang Hu, Wenbo Zhao, Peng Du, Yulei Zhang, Amiral...
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...