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DAC
1996
ACM
14 years 4 months ago
A Description Language for Design Process Management
A language for defining design discipline characteristics is proesign discipline characteristics such as abstraction levels, design object classifications and decompositions, desi...
Peter R. Sutton, Stephen W. Director
DAC
1996
ACM
14 years 4 months ago
Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance
Measured Equation of Invariance(MEI) is a new concept in computational electromagnetics. It has been demonstrated that the MEI technique can be used to terminate the meshes very c...
Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II
DAC
1996
ACM
14 years 4 months ago
Software Development in a Hardware Simulation Environment
Concurrent verification of hardware and software as part of the development process can shorten the time to market of complex systems. The objectives of the Virtual CPU approach i...
Benny Schnaider, Einat Yogev
DAC
1996
ACM
14 years 4 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano
DAC
1996
ACM
14 years 4 months ago
Post-Layout Optimization for Deep Submicron Design
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emu...
DAC
1996
ACM
14 years 4 months ago
Tutorial: Design of a Logic Synthesis System
Logic synthesis systems are complex systems and algorithmic research in synthesis has become highly specialized. This creates a gap where it is often not clear how an advance in a...
Richard L. Rudell
DAC
1996
ACM
14 years 4 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DAC
1996
ACM
14 years 4 months ago
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
Val Popescu, Bill McNamara