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    DAC
    2008
    ACM
    101views Computer Architecture» more  DAC 2008»
    Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications
    14 years 1 months ago
    Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications
    Download  medianetlab.ee.ucla.edu
    Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaa...
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    DAC
    2008
    ACM
    128views Computer Architecture» more  DAC 2008»
    Techniques for fully integrated intra-/inter-chip optical communication
    14 years 1 months ago
    Techniques for fully integrated intra-/inter-chip optical communication
    Download  infoscience.epfl.ch
    Claudio Favi, Edoardo Charbon
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    DAC
    2008
    ACM
    112views Computer Architecture» more  DAC 2008»
    IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
    14 years 1 months ago
    IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
    Download  www.stanford.edu
    Sung-Boem Park, Subhasish Mitra
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    DAC
    2008
    ACM
    132views Computer Architecture» more  DAC 2008»
    Application mapping for chip multiprocessors
    14 years 1 months ago
    Application mapping for chip multiprocessors
    Download  www.cse.psu.edu
    The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
    Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
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    DAC
    2008
    ACM
    179views Computer Architecture» more  DAC 2008»
    SHIELD: a software hardware design methodology for security and reliability of MPSoCs
    14 years 1 months ago
    SHIELD: a software hardware design methodology for security and reliability of MPSoCs
    Download  www.inf.pucrs.br
    Security of MPSoCs is an emerging area of concern in embedded systems. Security is jeopardized by code injection attacks, which are the most common types of software attacks. Prev...
    Krutartha Patel, Sri Parameswaran
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    DAC
    2008
    ACM
    162views Computer Architecture» more  DAC 2008»
    Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
    14 years 1 months ago
    Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
    Download  users.eecs.northwestern.edu
    Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
    Min Ni, Seda Ogrenci Memik
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    DAC
    2008
    ACM
    168views Computer Architecture» more  DAC 2008»
    Faster symmetry discovery using sparsity of symmetries
    15 years 13 days ago
    Faster symmetry discovery using sparsity of symmetries
    Download  www.eecs.umich.edu
    Many computational tools have recently begun to benefit from the use of the symmetry inherent in the tasks they solve, and use general-purpose graph symmetry tools to uncover this...
    Paul T. Darga, Karem A. Sakallah, Igor L. Markov
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    DAC
    2008
    ACM
    143views Computer Architecture» more  DAC 2008»
    Tera-scale computing and interconnect challenges
    15 years 13 days ago
    Tera-scale computing and interconnect challenges
    Download  www.cc.gatech.edu
    Jerry Bautista
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    DAC
    2008
    ACM
    142views Computer Architecture» more  DAC 2008»
    On the role of timing masking in reliable logic circuit design
    15 years 13 days ago
    On the role of timing masking in reliable logic circuit design
    Download  www.eecs.umich.edu
    Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
    Smita Krishnaswamy, Igor L. Markov, John P. Hayes
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    DAC
    2008
    ACM
    109views Computer Architecture» more  DAC 2008»
    An integrated nonlinear placement framework with congestion and porosity aware buffer planning
    15 years 13 days ago
    An integrated nonlinear placement framework with congestion and porosity aware buffer planning
    Download  www.cerc.utexas.edu
    Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
    Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
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