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DATE
2000
IEEE
75views Hardware» more  DATE 2000»
14 years 3 months ago
Layout Compaction for Yield Optimization via Critical Area Minimization
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
Youcef Bourai, C.-J. Richard Shi
DATE
2000
IEEE
99views Hardware» more  DATE 2000»
14 years 3 months ago
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 3 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DATE
2000
IEEE
78views Hardware» more  DATE 2000»
14 years 3 months ago
HW/SW Codesign of an Engine Management System
The design process for an engine management system is presented. The functional specification of the system has been captured using C and C++ as specification languages. The val...
Massimo Baleani, Alberto Ferrari, Alberto L. Sangi...
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
14 years 3 months ago
Automatic Abstraction for Worst-Case Analysis of Discrete Systems
c Abstraction for Worst-Case Analysis of Discrete Systems Felice Balarin Cadence Berkeley Laboratories Recently, a methodology for worst-case analysis of discrete systems has been...
Felice Balarin
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
14 years 3 months ago
A Discrete-Time Battery Model for High-Level Power Estimation
In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-t...
Luca Benini, Giuliano Castelli, Alberto Macii, Enr...