DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
DATE
2000
IEEE
14 years 6 months ago
2000
IEEE