Sciweavers

DATE
2006
IEEE
96views Hardware» more  DATE 2006»
14 years 5 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
DATE
2006
IEEE
136views Hardware» more  DATE 2006»
14 years 5 months ago
Defect tolerance of QCA tiles
Quantum dot Cellular Automata (QCA) is one of the promising technologies for nano scale implementation. The operation of QCA systems is based on a new paradigm generally referred ...
Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 5 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 5 months ago
Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint
The energy-aware design for electronic systems has been an important issue in hardware and/or software implementations, especially for embedded systems. This paper targets a synth...
Heng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
14 years 5 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
DATE
2006
IEEE
145views Hardware» more  DATE 2006»
14 years 5 months ago
Improved offset-analysis using multiple timing-references
In this paper, we present an extension to existing approaches that capture and exploit timing-correlation between tasks for scheduling analysis in distributed systems. Previous ap...
Rafik Henia, Rolf Ernst
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 5 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
14 years 5 months ago
Microarchitectural floorplanning under performance and thermal tradeoff
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...
Michael B. Healy, Mario Vittes, Mongkol Ekpanyapon...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 5 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles